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DATA SHEET
MOS INTEGRATED CIRCUIT
PD8670A
7400 PIXELS CCD LINEAR IMAGE SENSOR
The PD8670A is a high sensitive and high-speed CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal. The PD8670A is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers the photo signal electrons of 7400 pixels separately in odd and even pixels. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 600 dpi/A3 high-speed digital copiers, multi-function products and so on.
FEATURES
* Valid photocell * Photocell pitch * Photocell size * Resolution * Data rate * Output type * High sensitivity * Low image lag * Power supply * On-chip circuits : : 7400 pixels : 4.7 m : 4.7 x 4.7 m2 : 24 dot/mm (600 dpi) A3 (297 x 420 mm) size (shorter side) : 44 MHz MAX. (22 MHz/1 output) : 2 outputs in-phase operation, and out of phase also supported : 17.0 V/lx*s TYP. (Light source: Daylight color fluorescent lamp) : 1 % MAX. : +12 V : Reset feed-through level clamp circuits Voltage amplifiers
* Peak response wavelength : 550 nm (green) * Drive clock level : CMOS output under +5 V operation
ORDERING INFORMATION
Part Number Package CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
PD8670ACY
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. S17147EJ1V0DS00 (1st edition) Date Published August 2004 NS CP (K) Printed in Japan
2004
PD8670A
DIFFERENCE BETWEEN PD8670ACY AND PD3747D
Part Item
PD8670ACY
2 outputs out of phase or in phase TYP. 17 V/lx*s
PD3747D
2 outputs in phase only TYP. 19 V/lx*s
Referential Page
Features
Output type Sensitivity (Daylight color fluorescent lamp)
1
Ordering information Pin configuration Block diagram Application circuit example Absolute maximum ratings
Package Input clock
32-pin plastic DIP
22-pin ceramic DIP (CERDIP)
CP1, CP2 separated, R1, R2 separated, 2L1, 2L2 separated
(Output: in/out of phase)
CP common, R common, 2L common
(Output: in phase) 2SA1005, 2SC945 -25 to +55C
4 3 21
Equivalent circuit Tr. Operating ambient temperature Storage temperature
2SA1206, 2SC1842 0 to +60C
5
-40 to +70C Addition of specifications (from 4.5 V to 5.8 V)
-40 to +100C -
Recommended operating condition Electrical characteristics
Each clock amplitude
ADS, DSNU, DR1, DR2 RF RFTN
Change of specifications
-
6
TYP. 17 V/lx*s Addition of PRFTN, RFTN1, RFTN2
TYP. 19 V/lx*s Only RFTN
td
TYP. 13 ns Addition of min. max.
TYP. 14 ns
bit, line, shot
Input pin capacitance Capacitance
Addition of condition (t6) Change of specification Addition of note
- - 7
Timing chart
Operation
Addition of out-of-phase timing chart
-
8, 9
t6 t10 t13, t16, t17 Close point Definitions Recommended soldering condition Package drawing Package Cap From CCD to bottom of package From CCD to top of cap VOS, RFTN Partial heating method -
MIN. 5 ns MIN. 0 ns MAX. 10000 ns Change of specifications Additional item 350C or blow, 3 seconds or less
MIN. 0 ns MIN. t3 - - - 300C or blow, 3 seconds or less
12, 14
14 15 19 24
32-pin plastic DIP Plastic cap 0.7t 2.45 0.3 mm
22-pin ceramic DIP (CERDIP) Glass cap 0.7t 2.38 0.3 mm
23
(2.0) mm
(1.95) mm
Remark
TA = +25C, VOD = 12 V
2
Data Sheet S17147EJ1V0DS
PD8670A
BLOCK DIAGRAM
GND
CP2
30
R2
29
2L2
28
22
24
12
23
31
VOUT2 (Even)
32
CCD analog shift register Transfer gate
S7399
S7400
OB96
OB1
D12
D6
D7
***
***
***
***
22
TG
S1
D1
Transfer gate
VOUT1 (Odd)
1
CCD analog shift register
2 VOD
S2
3
4
5
9
10
11
CP1
R1
2L1
11
21
GND
Data Sheet S17147EJ1V0DS
3
PD8670A
PIN CONFIGURATION (Top View)
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400)) * PD8670ACY
Output signal 1 (Odd) Output drain voltage Reset feed-through level clamp clock 1 Reset gate clock 1 Last stage shift register clock 1 Internal connection Internal connection No connection Shift register clock 1-1 Shift register clock 2-1 Ground
Internal connection Internal connection No connection
No connection No connection
VOUT1 VOD
1 2 3 4 5 6 7 8 9 10 11
12 13 14
15 16
32 31 30 29 28 27 26 25 24 23 22
21 20
19
18
17
VOUT2 GND
Output signal 2 (Even) Ground Reset feed-through level clamp clock 2 Reset gate clock 2 Last stage shift register clock 2 Internal connection Internal connection No connection Shift register clock 2-2 Shift register clock 1-2 Transfer gate clock
Internal connection Internal connection
No connection
No connection
No connection
CP1
CP2 R2 2L2
IC IC NC
R1
2L1
IC IC NC
11 21
GND
IC IC NC
NC NC
22 12
TG
IC IC
NC
NC
NC
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26 and 27 (IC) unconnected. 2. Connect the No connection pins (NC) to GND.
PHOTOCELL STRUCTURE DIAGRAM
3.2 m
1.5 m
4.7 m
Channel stopper
Aluminum shield
4
Data Sheet S17147EJ1V0DS
PD8670A
ABSOLUTE MAXIMUM RATINGS (TA = +25C)
Parameter Output drain voltage Shift register clock voltage Last stage shift register clock voltage Reset gate clock voltage Transfer gate clock voltage Reset feed-through level clamp clock voltage Operating ambient temperature Storage temperature
Note
Symbol VOD V 1, V 2 V 2L V R V TG V CP TA Tstg
Ratings -0.3 to +14.0 -0.3 to +8.0 -0.3 to +8.0 -0.3 to +8.0 -0.3 to +8.0 -0.3 to +8.0 0 to +60 -40 to +70
Unit V V V V V V C C
Note Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25C)
Parameter Output drain voltage Shift register clock high level Shift register clock low level Last stage shift register clock high level Last stage shift register clock low level Reset gate clock high level Reset gate clock low level Reset feed-through level clamp clock high level Reset feed-through level clamp clock low level Transfer gate clock high level Transfer gate clock low level Shift register clock amplitude Symbol VOD V 1H, V 2H V 1L, V 2L V 2LH V 2LL V RH V RL V CPH V CPL V TGH V TGL V 1_pp, V 2_pp Last stage shift register clock amplitude Reset gate clock amplitude Reset feed-through level clamp clock amplitude Transfer gate clock amplitude Data rate V 2L_pp V R_pp V CP_pp V TG_pp 2f R f < 10 MHz/ch f 10 MHz/ch Conditions MIN. 11.4 4.5 -0.3 4.5 -0.3 4.5 -0.3 4.5 -0.3 4.5 -0.3 4.0 4.5 4.5 4.5 4.5 4.5 1 TYP. 12.0 5.0 0 5.0 0 5.0 0 5.0 0 5.0 0 5.0 5.0 5.0 5.0 5.0 5.0 2 MAX. 12.6 5.5 +0.5 5.5 +0.5 5.5 +0.5 5.5 +0.5 5.5 +0.5 5.8 5.8 5.8 5.8 5.8 5.8 44 Unit V V V V V V V V V V V V V V V V V MHz
Data Sheet S17147EJ1V0DS
5
PD8670A
ELECTRICAL CHARACTERISTICS
TA = +25C, VOD = 12 V, f R = 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 Vp-p, light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter Saturation voltage Saturation exposure Photo response non-uniformity Average dark signal Dark signal non-uniformity Power consumption Output impedance Response Image lag Offset level
Note 1 Note 2
Symbol Vsat SE PRNU ADS DSNU PW ZO RF IL VOS td TTE RI
Test Conditions
MIN. 1.5
TYP. 2.0 0.10 5.0 1.0 16.0 350 0.2 17.0 0.5 4.7 13.0 98 1.0 550 125 1000 +0.4 -0.4 +0.2 2.6 2.0 8.0
MAX. - - 10.0 6.0 28.0 420 0.3 20.4 1.0 5.7 15.0 - 4.0 - - - - +0.2 +0.7 - - - -
Unit V lx*s % mV mV mW k V/lx*s % V ns % % nm times times V V V mV mV mV
Daylight color fluorescent lamp VOUT = 500 mV Light shielding Light shielding
- - - - - -
Daylight color fluorescent lamp VOUT = 500 mV
13.6 - 3.7
Output fall delay time
VOUT = 500 mV VOUT = 1 V, data rate = 44 MHz VOUT = 500 mV
11.0 94 0 -
Total transfer efficiency Register imbalance Response peak Dynamic range
Note 1
DR1 DR2
Vsat/DSNU Vsat/ bit, t6 20 ns Light shielding, t4 = 5 ns
- - - -1.0 -0.3 - - - -
Reset feed-through noise
PRFTN RFTN1 RFTN2
Random noise
bit line shot
Light shielding, bit clamp mode Light shielding, line clamp mode
t6 = 5 ns t6 20 ns t6 5 ns t6 5 ns
Shot noise
VOUT = 500 mV, bit clamp mode
10.0
mV
Notes 1. Refer to 13 and 14 of DEFINITION OF CHARACTERISTIC ITEMS. 2. When the fall time of 2L (t2') is the TYP. value (refer to TIMING CHART 5, 6). Note that VOUT1 and VOUT2 are the outputs of the two steps of emitter-follower shown in APPLICATION CIRCUIT EXAMPLE.
6
Data Sheet S17147EJ1V0DS
PD8670A
INPUT PIN CAPACITANCE (TA = +25C, VOD = 12 V)
Parameter Shift register clock pin capacitance 1 Symbol C
Note 1
Pin name
Pin No. 9 23 10 24 5 28 4 29 3 30 22
MIN. 225 200 200 225 4 4 4 4 7 7 240
TYP. 250 220 220 250 5 5 5 5 8 8 270
MAX. 275 240 240 275 6 6 6 6 9 9 300
Unit pF pF pF pF pF pF pF pF pF pF pF
11 12 21 22 2L1 2L2 R1 R2 CP1 CP2 TG
Shift register clock pin capacitance 2
C 2Note
Last stage shift register clock pin capacitance
C L
Reset gate clock pin capacitance
C R
Reset feed-through level clamp clock pin capacitance
C CP
Transfer gate clock pin capacitance
C TG
Note C 1, C 2 are equivalent capacitance with driving device, including the co-capacitance between 1 and 2. Remark Pins 9 and 23 ( 11 and 12), Pins 10 and 24 ( 21 and 22) aren't each connected inside of the device.
Data Sheet S17147EJ1V0DS
7
7531
7533
7535
7537
7539 7538 7540
VOUT1
12 22 2L2
R2
CP2
7532 7534 7536 7542 126 128 130 132 134 136 138 30 32 34 36 2 4 6
VOUT2
7541
125
127
129
131
133
135
137
29
31
33
35
1
3
5
8
TIMING CHART 1 (Bit clamp mode, Out of phase operation)
TG
11 21 2L1
R1
CP1
Data Sheet S17147EJ1V0DS
PD8670A
Note
Dummy cell (32 pixels)
Optical black (96 pixels) Invalid photocell (6 pixels)
Valid photocells (7400 pixels) Invalid photocell (6 pixels)
Note Set the R1, R2, CP1 and CP2 to low level during this period.
TIMING CHART 2 (Line clamp mode, Out of phase operation)
TG
11 21 2L1
R1
CP1
7531 7533 7535 7537 7539 7538 7540 7541 7542
Data Sheet S17147EJ1V0DS
125
127
129
131
133
135
VOUT1
12 22 2L2
R2
CP2
7532 7534 7536 126 128 130 132 134 136 138 30 32 34 36 2 4 6
VOUT2
137
29
31
33
35
1
3
5
PD8670A
Note
Dummy cell (32 pixels)
Optical black (96 pixels) Invalid photocell (6 pixels)
Valid photocells (7400 pixels) Invalid photocell (6 pixels)
Note Set the R1, R2, CP1 and CP2 to low level during this period.
9
7531
7533
7535
7537
7539 7540
VOUT1
7532
7534
7536
7538
VOUT2
Note
Dummy cell (32 pixels)
Optical black (96 pixels) Invalid photocell (6 pixels)
Valid photocells (7400 pixels) Invalid photocell (6 pixels)
7542
126
128
130
132
134
136
138
30
32
34
36
2
4
6
7541
125
127
129
131
133
135
137
29
31
33
35
1
3
5
10
Data Sheet S17147EJ1V0DS
TIMING CHART 3 (Bit clamp mode, In phase operation)
TG
11, 12
21, 22
2L1, 2L2
R1, R2
CP1, CP2
PD8670A
Note Set the R1, R2, CP1 and CP2 to low level during this period.
TIMING CHART 4 (Line clamp mode, In phase operation)
TG
11, 12
21, 22
2L1, 2L2
R1, R2
7532
7534
7536
7538
7540
VOUT2
Note
Dummy cell (32 pixels)
Optical black (96 pixels) Invalid photocell (6 pixels)
Valid photocells (7400 pixels) Invalid photocell (6 pixels)
7542
126
128
130
132
134
136
138
30
32
34
36
2
4
6
Data Sheet S17147EJ1V0DS
CP1, CP2
7531 7533 7535 7537 7539 7541
125
127
129
131
133
135
VOUT1
137
29
31
33
35
1
3
5
PD8670A
Note Set the R1, R2, CP1 and CP2 to low level during this period.
11
PD8670A
TIMING CHART 5 (Bit clamp mode)
t1 t2
11
90% 10% 90% 10% t1' t2'
21
2L1
90% 10% t4 t3 t5 t6
R1
90% 10% t10 t8 t7 t9 t11
CP1
90% 10%
td VOUT1
VOS 10%
Symbol t1, t2 t1', t2' t3 t4, t5 t6 t7 t8, t9 t10 t11
MIN. 0 0 10 0 5 5 0 0 0
TYP. 50 5 125 5 125 125 5 125 250
MAX. - - - - - - - - -
Unit ns ns ns ns ns ns ns ns ns
Caution This shows timing chart of VOUT1 side (11, 21, 2L1, R1, CP1, VOUT1). The timing chart of VOUT2 side (12, 22, 2L2, R2, CP2, VOUT2) is equal.
12
Data Sheet S17147EJ1V0DS
PD8670A
TIMING CHART 6 (Line clamp mode)
t1 t2
11
90% 10% 90% 10% t1' t2'
21
2L1
90% 10% t4 t3 t5 t12
R1
90% 10%
CP1
"L"
td VOUT1
VOS 10%
Symbol t1, t2 t1', t2' t3 t4, t5 t12
MIN. 0 0 10 0 5
TYP. 50 5 125 5 250
MAX. - - - - -
Unit ns ns ns ns ns
Caution This shows timing chart of VOUT1 side (11, 21, 2L1, R1, CP1, VOUT1). The timing chart of VOUT2 side (12, 22, 2L2, R2, CP2, VOUT2) is equal.
Data Sheet S17147EJ1V0DS
13
PD8670A
TIMING CHART 7 (Bit clamp mode, Line clamp mode)
t14 90% 10% t16 t13 t15
TG
11
90%
90%
21, 2L1
t17 t4 t3 t5 t6
R1
90% 10% t10 t8 t7 t9 t11
CP1
Note
90% 10%
Note Set the R and CP to low level during this period.
Symbol t3 t4, t5 t6 t7 t8, t9 t10 t11 t13 t14, t15 t16, t17 MIN. 10 0 5 5 0 0 0 1000 0 200 TYP. 125 5 125 125 5 125 250 1500 50 300 MAX. - - - - - - - 10000 - 10000 Unit ns ns ns ns ns ns ns ns ns ns
Caution This shows timing chart of VOUT1 side (11, 21, 2L1, R1, CP1, VOUT1). The timing chart of VOUT2 side (12, 22, 2L2, R2, CP2, VOUT2) is equal.
14
Data Sheet S17147EJ1V0DS
PD8670A
11, 21 cross points
11
11, 2L1 cross points
11
1.5 V or more
1.5 V or more
1.5 V or more
21
2L1
0 V or more
12, 22 cross points
12
12, 2L2 cross points
12
1.5 V or more
1.5 V or more
1.5 V or more
22
2L2
0 V or more
Remark Adjust cross points of ( 11, 21), ( 11, 2L1), ( 12, 22) and ( 12, 2L2) with input resistance of each pin.
11, 12, 21, 22, 2L1, 2L2 clock width
0 ns or more
11, 12, 21, 22, 2L1, 2L2
4.5 V
0.5 V
0 ns or more
Data Sheet S17147EJ1V0DS
15
PD8670A
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula.
x x 100 x x: maximum of xj - x
7400
PRNU (%) =
x=
j=1
xj
VOUT
7400
xj: Output voltage of valid pixel number j
Register dark DC level
x x
4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
7400 j=1
dj
dj: Dark signal of valid pixel number j
ADS (mV) =
7400
16
Data Sheet S17147EJ1V0DS
PD8670A
5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula.
DSNU (mV): maximum of dj - ADS j = 1 to 7400 dj: Dark signal of valid pixel number j
VOUT
ADS
Register dark DC level
DSNU
6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx*s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line.
TG
Light ON OFF
VOUT
V1
VOUT
IL (%) =
V1 x 100 VOUT
9. Total transfer efficiency : TTE The total transfer rate of CCD analog shift register. This is calculated by the following formula, it is difined by each output. TTE (%) = (1 - Vb / average output of all the valid pixels) x 100
Vb Va-1 : The last pixel output - 1 (Odd pixel: 7537th pixel) Va : The last pixel output (Odd pixel: 7539th pixel) Vb : The spilt pixel output (Odd pixel: 7541st pixel) Va-1 Va
Data Sheet S17147EJ1V0DS
17
PD8670A
10. Register imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels.
n
2 n
(V2j - 1 - V2j)
j=1
2
RI (%) =
1 n
Vj
j=1
n
x 100
n : Number of valid pixels Vj : Output voltage of each pixel
11. Random noise : Random noise is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding).
100
(mV) =
i=1
(Vi - V)
100
2
, V=
1
100
100 i = 1
Vi
Vi : A valid pixel output signal among all of the valid pixels
VOUT
V1
V2
line 1 line 2
V100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling). 12. Shot noise : shot Shot noise is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling in the light. This includes the random noise. The formula is the same with that of random noise.
...
line 100
...
18
Data Sheet S17147EJ1V0DS
PD8670A
13. Offset level : VOS DC level of output signal is defined as follows. 14. Reset feed-through noise and peak reset feed-through noise : RFTN and PRFTN RTFN is switching noise of R and CP. Reset feed-through noise (RFTN) and peak of RFTN (PRFTN) are defined as follows. <1> Bit clamp operation
2L1
R1 CP1
RFTN2
VOUT1
PRFTN RFTN1 VOS
Caution This shows timing of VOUT1 side (2L1, R1, CP1, VOUT1). The definition of VOUT2 side (2L2,
R2, CP2, VOUT2) is equal.
<2> Line clamp operation
2L1
R1 CP1
"L"
VOUT1
PRFTN RFTN1 VOS
Caution This shows timing of VOUT1 side (2L1, R1, CP1, VOUT1). The definition of VOUT2 side (2L2,
R2, CP2, VOUT2) is equal.
Data Sheet S17147EJ1V0DS
19
PD8670A
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25C)
8
2
4 1
Relative Output Voltage
2
1
0.5
Relative Output Voltage
0.25
0.2
0.1 0 10 20 30 40 50 Operating Ambient Temperature TA (C)
0.1 1 5 Storage Time (ms) 10
TOTAL SPECTRAL RESPONSE CHARACTERISTIC (without infrared cut filter and heat absorbing filter) (TA = +25C)
100
80
Response Ratio (%)
60
40
20
0 400 600 800 Wavelength (nm) 1000 1200
20
Data Sheet S17147EJ1V0DS
PD8670A
APPLICATION CIRCUIT EXAMPLE
+12 V
+5 V
PD8670A
B1
0.1 F 47 F/25 V
+5 V
1 2
VOUT1 VOD
VOUT2 GND
32 31 30 29 28 27 26 25
24
23
22 21
20 19
18
17
B2
0.1 F 10 F/16 V
10 F/16 V 0.1 F
CP1 R1 2L1
47 47 47
3 4 5 6 7 8
CP1 R1 2L1
IC IC NC
CP2 R2 2L2
IC IC NC
47 47 47
CP2 R2 2L2
11 21
2 2
9 10 11 12 13 14 15 16
11 21
GND IC IC NC NC NC
22 12 TG
IC IC NC NC NC
2
2
22 12
10
TG
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26 and 27 (IC) unconnected. 2. Connect the No connection pins (NC) to GND. Remark The inverters shown in the above application circuit example are the 74AC04.
Data Sheet S17147EJ1V0DS
21
PD8670A
B1, B2 EQUIVALENT CIRCUIT
+12 V
4.7 k 110 CCD VOUT 47 2SA1206
47 F/25 V 2SC1842
+
Output
1 k
22
Data Sheet S17147EJ1V0DS
PD8670A
PACKAGE DRAWING
PD8670CY, PD8670ACY CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (10.16 mm (400) )
(Unit : mm) 55.20.5 54.80.5 1st valid pixel 3.20.3 32
1
17
9.050.3 9.250.3
4
1 46.7 12.60.5
4
16 2.0 4.10.5
1.020.15
4.550.5
10.160.20 (2.0)
2
2.450.3 0.460.1 2.540.25 (5.42) 4.210.5
3
10.16 +0.70 -0.20
0.250.05
Name Plastic cap
Dimensions 52.2x6.4x0.8 (0.7 5)
Refractive index 1.5
1 1st valid pixel The center of the pin1 2 The surface of the CCD chip The top of the cap 3 The bottom of the package The surface of the CCD chip 4 Mirror finishied surface 5 Thickness of mirror finished surface
32C-1CCD-PKG10-2
Data Sheet S17147EJ1V0DS
23
PD8670A
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device
PD8670ACY : CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
Process Partial heating method Conditions Pin temperature : 350C or below, Heat time : 3 seconds or less (per pin)
Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap soiling and heat resistance. So the method cannot be guaranteed.
24
Data Sheet S17147EJ1V0DS
PD8670A
NOTES ON HANDLING THE PACKAGES
1 DUST AND DIRT PROTECTING
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don't either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used.
RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Ethyl Alcohol Methyl Alcohol Isopropyl Alcohol N-methyl Pyrrolidone Symbol EtOH MeOH IPA NMP
2 MOUNTING OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating
3 OPERATE AND STORAGE ENVIRONMENTS
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
4 ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. 2. 3. 4. 5. 6. Ground the tools such as soldering iron, radio cutting pliers of or pincer. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. Either handle bare handed or use non-chargeable gloves, clothes or material. Ionized air is recommended for discharge when handling CCD image sensor. For the shipment of mounted substrates, use box treated for prevention of static charges. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 M.
Data Sheet S17147EJ1V0DS
25
PD8670A
[ NOTE ]
26
Data Sheet S17147EJ1V0DS
PD8670A
NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.
Data Sheet S17147EJ1V0DS
27
PD8670A
* The information in this document is current as of August, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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